1. Field of the Invention
This invention relates to a low temperature, single side, multiple step orientation dependent etching process for the fabrication of three dimensional structures from silicon, and more particularly to the use of this process for the mass production of ink jet printheads.
2. Description of the Related Art
In the manufacture of semiconductor structures, it is frequently desirable to generate large recesses or holes in association with relatively shallow recesses, which may or may not interconnect. For example, an ink jet printhead may be made of a silicon channel plate and a heater plate. Each channel plate has a relatively large ink manifold/reservoir recess or opening and a set of parallel, shallow, elongated channel recesses connected to the reservoir at one end and open at the other end. When aligned and bonded with a heater plate, the recesses in the channel plate become the ink reservoir and the ink channels, as described more fully in U.S. Pat. No. 4,601,777 to Hawkins et al, the disclosure of which is incorporated herein by reference.
In such printheads, it is frequently desirable to form a relatively large or deep reservoir, which is often etched completely through a 10-30 mil thick &lt;1-0-0&gt; wafer, and small or shallow channels, which may be only 1-5 mils deep. One manner of forming such channel plates is by a one step method in which the reservoir and channels are patterned in a single plasma silicon nitride masking layer. The drawback of this method is that the channels are etched for the same length of time as the much larger reservoir and through-etched fill hole. This can result in loss of dimensional control because of the increased probability of the channel intercepting a defect in the wafer crystal. Also, the long etch time can cause the channel width to grow or in crease if the pattern is not accurately aligned with the &lt;1-1-0&gt; plane of the wafer. Another critical drawback of the single step process is the potential for intra-channel width variation resulting from slicing the wafer off the &lt;1-0-0&gt; axis. If there is an off axis condition in the plane of the wafer, long duration etching is likely to form channels wider at one end than the other or non-symmetrical about a centerline.
One method for overcoming the disadvantages of the single step process involves forming the channels and the reservoir in separate etching steps and then subsequently joining them by a variety of methods, such as isotropic etching, machining the silicon material between the reservoir and the channel, or use of a thick film layer on the heater plate that is patterned and etched to form ink flow bypasses. Generally, such a structure is formed by etching a plurality of reservoirs in a &lt;1-0-0&gt; silicon wafer first, and then accurately aligning the channels to the edge of the reservoir in a second lithography step, followed by etch mask delineation and a second short orientation dependent etching (ODE) step, sufficient to etch the depth of the plurality of associated channels. An advantage of such a process is enhanced control of channel dimensioning because the mask defining the channels will be undercut about one-tenth as much as would be the case when the channels and the reservoir are delineated simultaneously. The problem with such a two-step process is that it is difficult to do a second lithography step with an ODE etched wafer because of the large steps and/or etched through holes resulting from the first etching step. The resulting resist mask is nonuniform and this results in a nonuniformity of fine structures, such as the ink jet channels.
There is another two step process for forming the reservoir and the channels in a channel wafer by etching. This process is disclosed in U.S. Pat. No. 4,863,560 to Hawkins, the disclosure of which is incorporated herein by reference. In this process, the reservoir and any necessary throughholes are formed through a coarse silicon nitride mask as the wafer undergoes a relatively a long length etching process. Then the nitride mask is stripped to expose a previously patterned high temperature silicon oxide masking layer that is used in a subsequent, shorter duration, channel etching step. This process avoids the channel width variation problems associated with the previously described single step process, as the channels are formed during a very short etch duration step. The short etch time assures that rotational problems or taper resulting from mask misalignment are not likely to arise. However, the oxide masking layer for channel etching is a high temperature thermal oxide process, usually carried out at temperature of about 1100.degree. C., which can generate a high concentration of oxygen precipitate defects in the wafer and disruption of the crystal lattice. Such defects can cause loss of dimensional control, especially of the channels, and result in unusable channel plates. Also, the oxide layer is subject to considerable erosion in some anisotropic etches, for example, potassium hydroxide.
U.S. Pat. No. 4,063,271 to Bean et al discloses the use of low temperature oxides as a masking material for ODE separation of epitaxial layers forming semiconductor devices but does not disclose the use of such a material in the formation of large and fine structures in a silicon wafer.
U.S. Pat. No. 4,507,853 discloses the use of a low temperature oxide layer, usually in conjunction with a high temperature oxide layer, to insulate an element of a semiconductor from a metal conductor strip. The patent does not disclose formation of large and fine structures in a silicon wafer by such techniques.
U.S. Pat. No. 4,238,683 shows fabrication of gates of a silicon semiconductor by deposition of a silicon nitride layer followed by deposition of a low temperature oxide layer. The oxide and nitride layers are etched to form openings. The oxide layer is then partially removed to bare the nitride layer for subsequent removal. There is no disclosure of formation of fine and large structures in the silicon wafer.
U.S. Pat. No. 4,849,344 discloses the deposition of low temperature oxide for filling shallow grooves or trenches between epitaxial islands. The grooves are lined with a thin, thermally grown isolation oxide layer. The patent does not disclose the formation of fine and large structures by the use of low temperature oxides.